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Comparison of Dual-Rail and TMR Logic Cost Effectiveness and Suitability for FPGAs With Reconfigurable SEU Tolerance

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5 Author(s)

We compare four circuit methods for single event (SE) mitigation: single string with radiation-hardened flip flops, delay-guarded logic, dual-rail logic, and triple modular redundancy (TMR). Test results of the circuit methods at 180 nm are presented. We then describe a novel reprogrammable FPGA architecture which can be configured based on SE mitigation and performance needs, and we evaluate the candidate SE mitigation methods as to suitability for such architecture.

Published in:

IEEE Transactions on Nuclear Science  (Volume:56 ,  Issue: 1 )