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The idea for this special section started with the intention to archive the top papers from the First ACM/IEEE International Symposium on Networks on Chips (NOCS) in 2007. The first two papers tackle the tight power constraints of on-chip network design. The next two papers tackle routing protocol design in the the face of VLSI constraints of area and floorplanning. The last two papers present case studies of real NoC-based chip implementations.