By Topic

Overview and design directions for low-power circuits and architectures for digital signal processing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
T. Arslan ; Univ. of Wales, Cardiff, UK ; D. H. Horrocks ; A. T. Erdogan

Power dissipation is becoming a limiting factor in the realisation of VLSI systems. The principal reasons for this are maximum operating temperature and, for portable applications, battery life. Because of the relatively greater complexity, the power dissipation in Digital Signal Processing (DSP) applications is of special significance, and low-power design techniques are now emerging. This paper provides an overview of these techniques and aims to serve as a bibliography of the key papers relevant to low-power DSP design. In addition, the paper presents indications for potential design directions bearing in mind the architectural complexity and the speed requirements of today's systems. CMOS logic is assumed since this is currently the most commonly used VLSI technology due to its high degree of integration which is in turn allowed by its scaling properties and low power dissipation

Published in:

Low Power Analogue and Digital VLSI: ASICS, Techniques and Applications, IEE Colloquium on

Date of Conference:

2 Jun 1995