By Topic

Source and drain resistance studies of short-channel MESFETs using two-dimensional device simulators

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Yao-Tsung Tsai ; Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA ; Grotjohn, T.A.

A method for calculating the parasitic source and drain resistances in MESFETs using two-dimensional device simulators is discussed. The source and drain resistances are calculated using the power dissipation and the electron heating in the parasitic resistance regions of the device structure. The parasitic resistances are calculated as a function of both the gate and the drain bias voltages. The resistance calculation method for MESFETs has been applied to three semiconductor device simulators: a drift-diffusion method simulator, an energy transport method simulator, and a Monte Carlo particle method simulator

Published in:

Electron Devices, IEEE Transactions on  (Volume:37 ,  Issue: 3 )