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A low energy muon trigger for Icecube

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6 Author(s)
Bohm, C. ; Department of Physics, University of Stockholm, Sweden ; Kavianipour, Hossien ; Nygren, David ; Robson, Clyde
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A “Track Engine” (TE) concept has been developed for use with IceCube to maximize track-finding efficiency in the presence of noise. IceCube is a km-scale neutrino detector under construction at South Pole, now consisting of 40 strings of 60 Digital Optical modules (DOM) sensitive to Cherenkov light. Each DOM includes a large PMT that generates noise pulses at ∼500 Hz. The detection by a DOM of a pulse, noise or signal, generates a “Hit”. The full-scale IceCube will consist of 86 strings, and is expected to generate an average of approximately 13 random Hits during any 5μs window, the characteristic traversal time within the array of a relativistic muon. Data is currently acquired with a simple multiplicity trigger (SMT) requiring at least 16 DOM Hits, with the additional requirement that these Hits form local coincidence pairs (8 Hit pairs). However, this trigger is inefficient, especially for low energy muons that generate a minimum of light, but are of special interest for many experimental studies such as detecting signals from WIMP annihilation in the earth or sun. To increase efficiency for dim tracks, the TE examines all Hits, paired or not, and exploits topological features characteristic of straight line trajectories within the array to identify muons even in the presence of substantial noise. A single PC and FPGA combination is expected to handle the full IceCube Hit rate of 2.5 MHz with more than a factor two margin. The received Hits are time sorted in a PC and fed to a Xilinx ML507 FPGA board implementing the track engine algorithm. The FPGA solution was chosen, since it could be shown that the present algorithm cannot be implemented in software on one PC alone. The design reaches its high performance by an extensive pipelining of the calculations and operations, well designed and optimized network nodules in software and an extensive use of the fast, single-cycle delay Block RAM available in the FPGA.

Published in:
Nuclear Science Symposium Conference Record, 2008. NSS '08. IEEE

Date of Conference: 19-25 Oct. 2008

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