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A very low power and low signal 5 bit 50 M samples/s double sampling pipelined ADC for Monolithic Active Pixel Sensors in high energy physics and biomedical imaging applications

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7 Author(s)
Dahoumane, M. ; Institut pluridisciplinaire Hubert Curien (IPHC), 23, rue du Loess, 67037 Strasbourg France ; Bouvier, J. ; Dzahini, D. ; Martel, L.Gallin
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The use of CMOS Monolithic Active Pixel Sensors (MAPS) for high precision minimum ionizing particle tracking has been proven to be a viable and powerful novel experimental technique. Possible applications will strongly depend on a successful implementation of on-chip hit recognition and sparsification schemes. For this aim, a 5 bit very low power and low level signal analog to digital converter (ADC) using a double sampling switched capacitor technique has been implemented in 0.35µm CMOS technology. A non-resetting sample and hold stage is integrated. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of three successive 1.5 bit pipeline stages followed by a 2 bit flash stage. The prototype consists of 16 ADC double-channels; each one is sampling at 50 MS/s and dissipates only 1.38 mW at 2 V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1 µs. The size of the ADC is 80 µm × 1.4 mm. This corresponds to the pitch of 4 pixel columns in which each one is 20 µm wide and can be easily integrated in the MAPS.

Published in:

Nuclear Science Symposium Conference Record, 2008. NSS '08. IEEE

Date of Conference:

19-25 Oct. 2008