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Integrated circuits today rely on extensive reuse of IP bocks and macro cells to meet the demand for high performance system-on-chip. We propose a methodology for extracting timing models of IP blocks and macro cells for statistical timing analysis considering process variations and spatial correlations. We develop efficient models for capturing both inter-die and intra-die variations in device and interconnect parameters. Increasing spatial correlations in variability of the process parameters in subnanometer designs requires instance-specific characterization of these design blocks. We propose a novel technique for instance-specific calibration of precharacterized timing model. The proposed approach was evaluated on large industrial designs of 1.2- and 3.5-M gates in 65-nm technology and validated against SPICE for accuracy.