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A function-pipelined architecture and VLSI chip for MPEG video image coding

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3 Author(s)
Chen-Mie Wu ; Dept. of Electron. Eng., Nat. Taiwan Inst. of Technol., Taipei, Taiwan ; Zi-Hong Chou ; Yuan-Lin Chen

A function-pipelined architecture is presented for MPEG video image coding. Also, based on a 0.8 μm SPDM CMOS technology, a VLSI chip has been designed and implemented for such an architecture. The chip consists of 43,066 transistors and has a die size of 6,673 μm×5,260 μm (or 0.36 cm2). In the future, with such a VLSI chip, a coding processor will be developed for improving the performance of the MPEG video encoding system under development

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:41 ,  Issue: 4 )

Date of Publication:

Nov 1995

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