By Topic

B1. ESD protection of high speed / high frequency circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Benjamin Van Camp ; Sarnoff, USA

At a time when the downscaling of technology makes it increasingly difficult to meet the ESD specifications, new and evermore challenging applications make the job of the ESD engineer even more complex; many traditional solutions are rejected because they introduce too much capacitance, noise, etc. The goal of this workshop is to increase the awareness and insight of the ESD designers by discussing the most important figures of merit for both the ESD devices as well as the full ESD strategy, focusing on the protection of high speed interfaces. Both design and layout aspects will be discussed, comparing different protection techniques. We will compare all these trade-offs to figure out what are the remaining options in the shrinking tool box of the ESD engineer.

Published in:

Electrical Overstress/Electrostatic Discharge Symposium, 2008. EOS/ESD 2008. 30th

Date of Conference:

7-11 Sept. 2008