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We report on the ESD performance of dual well and triple well, silicide-blocked stacked NMOSFETs in a 45 nm CMOS technology. Triple well stacked NMOSFETs have a 1.5X higher HBM failure voltages compared to dual well designs. Further, we report on the effect of gate-biasing on the ESD performance of dual well, gate-silicided, silicide-blocked 2.5 V stacked NMOSFETs. For gate voltages (VGS) larger than 40% of the drain voltage (VDS) under the transient ESD conditions, the HBM failure voltage decreases with increasing gate voltage when applied on top gate with bottom gate grounded.