By Topic

Capacitance investigation of diode and GGNMOS for ESD protection of high frequency circuits in 45nm SOI CMOS technologies

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Junjun Li ; IBM Semicond. R&D Center, Essex Junction, VT ; Mitra, S. ; Hongmei Li ; Abou-Khalil, M.J.
more authors

S-parameter test structures from a 45 nm SOI CMOS technology show total capacitance per perimeter of poly-bounded ESD diodes ranges from ~0.35-0.42 fF/mum, and silicide-block (SBLK) bounded diodes show ~15-20% capacitance reduction. Floating-body or notched-silicon tied-body Gate-Silicided GGNMOS devices show total capacitance per width of ~0.65 fF/um for thin oxide devices, and ~0.72 fF/mum for thick oxide devices. Gate-Non-Silicided devices have ~20% higher capacitance because of increased junction area.

Published in:

Electrical Overstress/Electrostatic Discharge Symposium, 2008. EOS/ESD 2008. 30th

Date of Conference:

7-11 Sept. 2008