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A compact low-power VLSI transceiver for wireless communication

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4 Author(s)
Bang, S.H. ; Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA ; Joongho Choi ; Sheu, B.J. ; Chang, R.C.

A 3 V CMOS VLSI for dual-mode wireless communication systems has been designed and fabricated using the MOSIS scaleable CMOS technology. By using mixed analog and digital circuit design techniques, a single chip solution to baseband processing of data and supervisory audio tone signals in the analog transmission mode is possible. Key analog circuits include an anti-alias filter, two fifth-order low-pass filters, one sixth-order band-pass filter, an interpolator for sampling rate conversion, and two comparators. The digital modules perform data transmission and reception, error coding and decoding, as well as tone detection and regeneration. When implemented in the 2 μm CMOS technology from the MOSIS Service for low-cost low-power applications, the transceiver chip consumes less than 6 mW at receive-only mode. It is also quite suitable for battery-powered devices, such as portable terminals. Design technologies can be applied to future high-speed wireless transceiver design. The architecture and circuits described in this chip can be used in aggressively scaled technologies even with the supply voltage reduced toward 1 V if the threshold voltage is proportionally decreased

Published in:

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on  (Volume:42 ,  Issue: 11 )