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Architectures and algorithms for millisecond-scale molecular dynamics simulations of proteins

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1 Author(s)
David E. Shaw ; D. E. Shaw Research, USA

The ability to perform long, accurate molecular dynamics (MD) simulations involving proteins and other biological macromolecules could in principle lead to important scientific advances and provide a powerful new tool for drug discovery. A wide range of biologically interesting phenomena, however, occur over time scales on the order of a millisecond - several orders of magnitude beyond the duration of the longest current MD simulations. Our research group is currently building a specialized, massively parallel machine, called Anton, which should soon be capable of executing millisecond-scale MD simulations of proteins at an atomic level of detail. Antonpsilas highly accelerated execution of such simulations is attributable in large part to specialized logic for the high-speed calculation of pairwise interactions between particles and/or gridpoints separated by no more than some specified cutoff radius.In particular, each of Anton's 512 ASICs, which are implemented using 90-nm technology,includes a "high-throughput interaction subsystem" incorporating 32 highly specialized pipelines running at 800 MHz. During every cycle, each of these pipelines produces a pairwise-interaction result that would require approximately 50 arithmetic operations to calculate on a general-purpose processor. Novel algorithms and architectural features are used to greatly reduce the requirements for inter- and intra-chip communication, allowing Anton to feed these pipelines and collect their results at a speed sufficient to take advantage of the machine's computational power. The ASIC also includes a "flexible subsystem" based on eight programmable "geometry cores", each containing eight arithmetic pipelines. This talk will provide an overview of our work on parallel algorithms and machine architectures for high-speed MD simulation, with special attention to the respective roles of specialized vs. general-purpose hardware, and to the techniques used to minimize communication at various lev- - els within the system.

Published in:

2008 41st IEEE/ACM International Symposium on Microarchitecture

Date of Conference:

8-12 Nov. 2008