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5 GHz 11-Stage CML VCO with 40% Frequency Tuning in 0.13μm SOI CMOS

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3 Author(s)
Kim, D.D. ; Semicond. R&D Center, IBM, Hopewell Junction, NY ; Choongyeun Cho ; Jonghae Kim

This paper presents a manufacturable CML-based 11-stage VCO for digital system clock fabricated in 0.13 mum SOI CMOS. The 11-stage design enables quality oscillation, wide frequency tuning range, and process variability rejection. On average, the VCO exhibits 40% frequency tuning range from 4.23 to 6.35 GHz. The VCO phase noise is -129.8 dBc/Hz at 10 MHz offset in current-controlled measurements, and average FoMT(10%) is -178.1 dBc/Hz. Full 200 mm wafer scan result is presented along the phase noise measurement to demonstrate a statistical methodology.

Published in:

Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09. IEEE Topical Meeting on

Date of Conference:

19-21 Jan. 2009