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Fully parallel single and two-stage associative memories for high speed pattern matching

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3 Author(s)
Abedin, M.A. ; Dhaka Univ. of Eng. & Technol., Gazipur ; Koide, T. ; Mattausch, H.J.

A hardware realization of single and two-stage fully parallel associative memories for high speed reliable pattern matching is proposed. We have designed, fabricated and tested the single stage associative memory test chip designed in 0.35 mum two-poly, three-metal CMOS technology which gives very high speed pattern matching performance. But in some applications single stage search or single winner search makes the system less reliable. To increase the reliability of pattern matching system, we have also introduced a cascaded fully parallel associative memory with two-stage winner search. In two-stage pattern matching architecture we have used two different types of associative memories. One is based on the k-nearest-matches search and other one is a special type of associative memory in which winner search is done only among the activated reference patterns. The activation in the second associative memory is done by first associative memory after searching the k-nearest-matches. We have already designed, fabricated and tested the associative memories separately. The complete two-stage pattern matching system is tested here with MATLAB software and hardware realization is currently under the design process.

Published in:

Electrical and Computer Engineering, 2008. ICECE 2008. International Conference on

Date of Conference:

20-22 Dec. 2008

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