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An encoding scheme for high-speed single-ended parallel transceiver system is presented. Compared to the 50% I/O pin utilization of the conventional differential encoding, the proposed system employs 3-level differential coding to increase the utilization to 75% and 93% using a group of four and six conductors, respectively. The proposed coding scheme also reduces the effects of inter-symbol interference (ISI), removes reference ambiguity, and reduces power line fluctuations at the transmitter side. Using simple encoder/decoder, the proposed scheme enables multiple drivers at the transmitter to recycle the same current, reducing power consumption. To validate the proposed system, a parallel link was designed in 0.18 mum CMOS process. The chip implements the coding algorithm over four conductors and achieves a data rate of 4.2 Gb/s/pin while dissipating 17.1 mW/Gb/s.