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A Slew Controlled LVDS Output Driver Circuit in 0.18 \mu m CMOS Technology

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2 Author(s)
Tajalli, A. ; Microelectron. Syst. Lab., Ecole Polytech. Fed. de Lausanne, Lausanne ; Leblebici, Y.

This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50 fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation at low supply voltages using a conventional 0.18 mum CMOS technology feasible. The output driver circuit consumes 4.5 mA while driving an external 100 Omega resistor with an output voltage swing of VOD = 400 mV, achieving a normalized power dissipation of 3.42 mW/Gbps. The area of the LVDS driver circuit is 0.067 mm2 and the measured output jitter is sigmarms = 4.5 ps. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5 Gbps where the speed will be limited by the load RC time constant.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:44 ,  Issue: 2 )