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This paper presents a new parallel processing wire routing algorithm, which finds a quasi-minimum Steiner tree for multi-point connections in a VLSI chip or a PCB. A VHDL code is written to implement the algorithm on a prototype 4times4 and 8times8 single layer grid. Two methods are proposed for the design of processing element. The algorithm has been successfully tested on a XC2VP30 Virtex-II Pro XUPV2P development system. The algorithm can be easily extended to multi-layer grids. This algorithm is found to give better quality routes and higher speedups compared to other parallel routing algorithms. Also it yields orders of magnitude speedups over software implementation.
TENCON 2008 - 2008 IEEE Region 10 Conference
Date of Conference: 19-21 Nov. 2008