Skip to Main Content
In this paper, we propose a block least mean square algorithm with delayed weight adaptation for hardware implementation of finite impulse response (FIR) adaptive filters. We have referred to the proposed algorithm as delayed block least mean square (DBLMS) algorithm. Unlike the delayed least mean square (DLMS) algorithm, the DBLMS algorithm takes a block of L input samples and yields a block of L output in every training cycle. The simulation result shows that the DBLMS algorithm has convergence performance equivalent to that of the DLMS algorithm. We have exploited the parallelism inherent in the DBLMS algorithm to derive a highly concurrent systolic architecture for FIR adaptive filters. The proposed architecture can support L time higher sampling rate compared with the best of the existing pipelined designs and, therefore, it would involve less samples of adaptation delays and would provide a more efficient implementation of LMS-based adaptive filters.