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A digital signal processing based bit synchronizer and novel hardware efficient lock detector circuit for bi-phase data for Chandrayaan-1 mission

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4 Author(s)

The paper presents hardware efficient design of digital signal processing (DSP) based bit synchronizer and lock detector circuit for bi-phase data. The system is developed for one of the payload of Chandrayaan-I mission, and tested for its performance. Apart from the implementation, paper describes the mathematical modeling of bit synchronizer. The whole design is accommodated in a single Actel-1280 FPGA. A comparison has been carried out between the developed lock detector circuit and the traditional I2 - Q2 lock detector and results are presented here. Paper also highlights the programmable nature of the design and methods to reduce the hardware requirement.

Published in:

TENCON 2008 - 2008 IEEE Region 10 Conference

Date of Conference:

19-21 Nov. 2008