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The signal processing algorithms face many challenges in real-time applications because of their high computational complexity. Therefore, the major issues have been the enhancement of speed of the arithmetic units in general and multiplications and additions in particular. Double based number systems (DBNS) are increasingly gaining popularity for their capabilities of handling arithmetic operations efficiently. Even though DBNS schemes exhibit reasonably good performance for 8 bit multiplication, they are not efficient for higher bits .In this paper we introduce a new concept ldquotriple based number systems (TBNS) for performance enhancement of the multiplier of the digital signal Processors. Efficiency of this number system has been dealt with in details and a comparison between TBNS and DBNS clearly indicate the advantages of the former in terms of speed, hardware complexity and power dissipation. Different architectural models have been proposed. Finally, an architecture of high precision FIR filter has been presented which exploits the advantages of the TBNS scheme.