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A novel scheme to reduce test application time in circuits with full scan

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2 Author(s)
Pradhan, D.K. ; Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA ; Saxena, J.

This paper proposes a hybrid method of combining sequential testing with scan testing in circuits with full scan capability. One shortcoming of full scan testing of sequential circuits is the high test application time. The goal of our scheme is to obtain shorter test application times while achieving detection of both the classical stuck-at faults as well as nonclassical faults such as delay faults. An algorithm for test generation in this hybrid scheme is described. Experimental results demonstrating the effectiveness of our approach on ISCAS '89 sequential benchmark circuits are presented. Results for the stuck-at fault model and the transition fault model (which represents a simplified model for delay faults) are presented. Significant reduction in test application time is shown possible

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:14 ,  Issue: 12 )