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Chip to substrate interconnect density is continuously being scaled down to support the rapidly decreasing minimum feature size of IC components. At very fine interconnect pitches not many chip to substrate interconnects can meet the requirements of reliability and performance. One potential solution to improve the interconnect reliability is the use of compliant structures as interconnects. In this article a novel and flexible chip to substrate interconnect scheme that comprises of multiple metallic nanowires as nano interconnects is proposed. In the proposed scheme an individual flip chip interconnect pad on the chip comprises of multiple metallic nanowires, which bond to the substrate solder pad. Patterned micropads made of metallic nanowires (MMN) are fabricated on silicon substrate by electrodeposition in patterned nanoporous alumina (PNA) templates. High aspect ratio PNA templates are fabricated by selective anodization of an aluminum thin film patterned with SiO2. The PNA templates are then filled by copper metal electrodeposition. The aluminum that is underneath SiO2 is protected from anodization. I-V characteristics of MMN, Sn solder coated and reflowed MMN display ohmic behavior with extremely low resistance values of few m Â¿. Eutectic Sn-Pb solder and multiple copper nanowires based interconnect joint displays shear strength of 42 MPa which is comparable to conventional flip chip package joints.
Date of Conference: 9-12 Dec. 2008