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As data communication speed increases beyond 10 Gbps, designing for optimal signal integrity becomes critical to ensure reliable data. In the high speed board/package design, designers are trying to eliminate or minimize all the impedance mismatches along the high speed signal path. When multilayer board is used to increase the signal density, via structures are unavoidable to connect the signal, ground and power supply traces on different layers. High speed via transitions usually bring impedance discontinuities with them which will cause signal reflections and distortions compromising signal integrity. The deterioration of signal integrity will generate additional jitter and decrease the data eye opening ultimately jeopardizing the reliability of the data. This paper addresses designing for signal integrity at 10 Gbps by comparing the signal integrity of single ended and differential through-hole vias for the designer. In each case, the impedance mismatch at the via transition can be minimized by optimizing a few parameters such as pitch size, via diameter, via height, excess via stub, antipad size and ground via locations. The impacts of these parameters are investigated with the help for a full-wave electromagnetic simulation and verified by measurements.