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Optimization of the gate misalignment effects in graded channel DG FD SOI n-MOSFET with high - κ gate dielectrics

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3 Author(s)
Sharma, R.K. ; Dept. of Electron. Sci., Univ. of Delhi South Campus, New Delhi ; Gupta, M. ; Gupta, R.S.

In this paper, gate misalignment effect have been analyzed in nanoscale double gate (DG) fully depleted (FD) SOI n-MOSFETs, incorporating two important technological issues-graded channel engineering and high-kappa gate dielectrics, using 3-D device simulations. The present work provides a valuable design insight in the performance of nanoscale graded channel DG FD SOI n-MOSFET with high-kappa gate dielectrics incorporating gate misalignment effects and serve as an accurate tool to optimize key device parameters aiding technology development.

Published in:

Recent Advances in Microwave Theory and Applications, 2008. MICROWAVE 2008. International Conference on

Date of Conference:

21-24 Nov. 2008