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As field programmable gate arrays (FPGAs) become more widely used, security concerns have been raised regarding FPGA use for cryptographic, sensitive, or proprietary data. Storing or implementing proprietary code and designs on FPGAs could result in the compromise of sensitive information if the FPGA device was physically relinquished or remotely accessible to adversaries seeking to obtain the information. A hardware description language (HDL) FPGA architecture supporting dynamic reconfiguration through granular reconfiguration control is presented for use in security applications. Testing validates the reconfiguration results and compares power usage, timing, and area estimates from a conventional and Dynamically Reconfigurable FPGA (DRFPGA) model.