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Enabling Dynamic Voltage & Frequency Scaling in next-generation microprocessors: Thermal & reliability considerations

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2 Author(s)
Sai Ankireddi ; Sun Microsystems Inc., 4120 Network Circle, Santa Clara, CA 95054, USA ; David Copeland

With each advancing generation of process technology, the CPU power continues to rise, creating additional issues for thermal/mechanical packaging design. A common therme in next-generation CPU offerings will be the use of dynamic voltage and frequency. Scaling (DVFS) to manage the chip power during operation. With a DVFS policy, it becomes all the more important to study the potential impacts of imposed temporal variation in power on the thermo-mechanical reliability. In this study, we demonstrate a system identification approach for a practical CPU application and exemplify the trade-offs involved in creating a DVFS policy that is satisfactory to both thermal/mechanical reliability engineers and CPU design teams.

Published in:

2008 IEEE 9th VLSI Packaging Workshop of Japan

Date of Conference:

1-2 Dec. 2008