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Threshold-voltage instability of polymer thin-film transistor under gate-bias and drain-bias stresses

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6 Author(s)
Y. R. Liu ; School of Electronic and Information Engineering, South China University of Technology, Guangzhou, 510640, China ; J. L. Yu ; P. T. Lai ; Z. X. Wang
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Polymer thin-film transistors (PTFTs) based on MEH-PPV semiconductor are fabricated by spin-coating process and characterized. Gate-bias and drain-bias stress effects at room temperature are observed in the devices. The saturation current decreases and the threshold voltage shifts toward negative direction upon the gate-bias stress. However, the saturation current increases and the threshold voltage shifts toward positive direction upon the drain-bias stress. For variable bias stress conditions, carrier mobility is almost unchanged. The results suggest that the origin of threshold-voltage shift upon negative gate-bias stress is predominantly associated with holes trapped within the SiO2 gate dielectric or at the SiO2/Si interface due to hot-carrier emission under high gate-bias stress, while time-dependent charge trapping into the deep trap states in the channel region is responsible for the drain-bias stress effect in the PTFTs.

Published in:

Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on

Date of Conference:

8-10 Dec. 2008