By Topic

CMOS image sensors and camera-on-a-chip for low-light level biomedical applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Deen, M.J. ; Electr. & Comput. Eng. Dept., McMaster Univ., Hamilton, ON ; Desouki, M. ; Faramarzpour, Naser

With the advances in deep submicron CMOS technologies, CMOS-based active-pixel sensors (APS) have become a practical alternative to charge-coupled devices (CCD) imaging technology. Key advantages of CMOS image sensors are that they are fabricated in standard CMOS technologies, which allow full integration of the image sensor along with the analog and digital processing and control circuits on the same chip and that they are of low cost. Since there is a practical limit on the minimum pixel size (4~5 mum), then CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel. Such smart pixels truly show the potential of CMOS technology in imaging applications, especially for high-speed applications. This work discusses various active-pixel sensors (APS) and shows the feasibility of using the DC-level to increase the sensitivity of the pixel for low-level light applications. Avalanche-photodiodes (APDs) are described, in addition to a discussion of the breakdown mechanism and microplasma in avalanche breakdown for single photon APDs. A fully integrated, 16 times 16 pixel CMOS camera-on-a-chip, fabricated in a standard CMOS 0.18 mum technology is also shown in this work. The array is based on 256 APS with a pixel size of 20 mum times 30 mum, a fill-factor of 60% with all digital and analog blocks implemented on-chip.

Published in:

Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on

Date of Conference:

8-10 Dec. 2008