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A low power high speed ROIC design for 1024×1024 IRFPA with novel readout stage

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5 Author(s)
Chang Liu ; Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics, Peking University, China ; Wengao Lu ; Zhongjian Chen ; Haimei Bian
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A low power high speed Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024 times 1024 image system. Ripple integration and readout scheme as well as highly efficient power management are introduced to this design in order to decrease total power. To further increase the readout speed while decrease the power dissipation, a novel readout stage is proposed and adopted in this circuit. By using the new structure, the ROIC achieves a data rate of 10 M/s per channel, with the total power dissipation of 56 mW.

Published in:

Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on

Date of Conference:

8-10 Dec. 2008