An embedded ultra low power nonvolatile memory in a standard CMOS logic process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mum 1P4M standard CMOS logic process and the core area is 0.06 mm
²
. The measured results indicate that the typical write/erase time is 10 ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 muA for program and 1.2 muA for read at a 1.6 V power supply.