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Performance evaluation is critical for the minimization of design cost. It consists of two parts: modeling the underlying hardware engine and evaluating the performance of the application code for the model developed in the first part. In this paper, we propose a new parameterized model for application-specific architectures and present a retargetable scheduler for performance evaluation. The model, different from those proposed previously, reflects comprehensive architectural characteristics that affect hardware parallelism. The scheduler, distinguished from previous ones, takes into account not only functional and storage unit resources but also interconnect resources during the performance evaluation. The new architecture model, together with the retargetable scheduler, enables designers to accurately evaluate the performance of a variety of ASIC and ASIP architectures.