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Very-high speed control of an FPGA-based finite-element-analysis permanent magnet synchronous virtual motor drive system

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3 Author(s)
Dufour, C. ; Opal-RT Technol., Montreal, QC ; Blanchette, H. ; Belanger, J.

Presented in this paper are the results of tests involving high-speed closed-loop control of a virtual permanent magnet synchronous motor (PMSM) drive implemented on a field-programmable gate array (FPGA) card, connected to an external controller. Three types of motor drive models are actually implemented on the FPGA card of the RT-LAB based real-time simulator used: a Park (d-q) model along with two different implementations of finite element analysis (FEA) based models. The first FEA model, previously published, is an FPGA implementation of a FEA model with an inductance calculation routine running on an associated CPU of the real-time simulator. The second FEA model has its inductance routine coded in the FPGA. One of the main objectives of the paper will be to compare the performance of the two FEA models. By virtue of the faster, FPGA-located, inductance routine update rate of the new model, it is expected that its precision at very high speed will be greater than the previous model, which was shown to be limited to 400 Hz electric frequency.

Published in:

Industrial Electronics, 2008. IECON 2008. 34th Annual Conference of IEEE

Date of Conference:

10-13 Nov. 2008