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A system-on-a-chip (SoC) built with embedded intellectual property (IP) cores offers attractive methodology design reuse, reconfigurability, and customizability. However, the integration of the design-for-testability (DfT) structures of the IP cores in these complex SoCs presents daunting challenges to designers and ultimately affects the time-to-market goals. In this paper, we introduce a design methodology to reduce the time to market by taking core test data from the design environment and automatically generating DfT structures that can easily be integrated into the SoC. A novel automated synthesis methodology to generate an SoC built-in self-test (BIST) to test the IP and custom logic cores is proposed. The proposed technique, i.e., NonExclusive Xor Test of 2D linear feedback shift register (NEXT 2D LFSR), is modeled after the principle of configurable 2D LFSR design, which generates a deterministic sequence of test vectors for random-vector-resistant faults and then random test vectors for random-vector-detectable faults. The basis of this method is to explore the design solution space for optimal 2D LFSR while embedding the test patterns by nonexclusively considering xor gates as the conventional LFSR does but including a simple logic solution for minimal hardware optimization. Moreover, the proposed approach is capable of optimizing the 2D LFSRs with consideration of the don't-care bits in the incompletely specified test patterns.