Skip to Main Content
A design methodology and protection strategy for ESD charged-device-model (CDM) robust digital systems is presented using a scalable postbreakdown transistor macromodel for 90- and 130-nm technologies. The macromodel was implemented in a design tool to aid reliable chip design and used to predict function failure in three different system-on-chip design examples. Simulations agree well with failure analysis observations, verifying the validity of the macromodel. A ldquocorrect-by-constructionrdquo protection strategy for overcoming induced ESD-CDM events is also proposed. No ESD-CDM-related function failures are observed for product chips protected with this strategy.