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A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM

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23 Author(s)
Miyano, S. ; Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan ; Numata, K. ; Sato, K. ; Yabe, T.
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An 8 Mb embedded DRAM has been developed. The salient feature of this embedded DRAM is page fault tolerance. Accessing across different pages can be performed using a minimum column cycle. This feature is achieved by placing a data latch and a transfer gate between the bit line sense amplifier and the column select gate. This DRAM can be reconfigured as separated 2 Mb units when it is embedded as a macro cell of an ASIC library

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Solid-State Circuits, IEEE Journal of  (Volume:30 ,  Issue: 11 )