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Clock buffer chip with multiple target automatic skew compensation

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2 Author(s)
Watson, R.B. ; Digital Semicond. Div., Digital Equipment Corp., Hudson, MA, USA ; Iknaian, R.B.

This paper describes the application of a digital delay locked loop that compensates for variable delays on the clock chip, printed circuit board clock traces, and the clock systems on multiple ASICs. For a computer system consisting of nine PC boards (“modules”) plugged into a back plane with two clock chips per board and six ASICs per clock chip, a locking range of 25-150 MHz was achieved with a maximum skew in the system of less than 1 ns

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:30 ,  Issue: 11 )