Referenced Items are not available for this document.
This paper describes the application of a digital delay locked loop that compensates for variable delays on the clock chip, printed circuit board clock traces, and the clock systems on multiple ASICs. For a computer system consisting of nine PC boards (“modules”) plugged into a back plane with two clock chips per board and six ASICs per clock chip, a locking range of 25-150 MHz was achieved with a maximum skew in the system of less than 1 ns
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:30
,
Issue:
11
)
Date of Publication: Nov 1995
- Page(s):
- 1267 - 1276
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 5173166
- Digital Object Identifier :
- 10.1109/4.475715
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Nov 1995
- Sponsored by :
- IEEE Solid-State Circuits Society
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