By Topic

Clock buffer chip with multiple target automatic skew compensation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Watson, R.B. ; Digital Semicond. Div., Digital Equipment Corp., Hudson, MA, USA ; Iknaian, R.B.

This paper describes the application of a digital delay locked loop that compensates for variable delays on the clock chip, printed circuit board clock traces, and the clock systems on multiple ASICs. For a computer system consisting of nine PC boards (“modules”) plugged into a back plane with two clock chips per board and six ASICs per clock chip, a locking range of 25-150 MHz was achieved with a maximum skew in the system of less than 1 ns

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:30 ,  Issue: 11 )