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Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 ps jitter

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5 Author(s)
Novof, I.I. ; Microelectron. Div., IBM Corp., Essex Junction, VT, USA ; Austin, J. ; Kelkar, R. ; Strayer, D.
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A fully integrated phase-locked loop (PLL) in a digital 0.5 μm CMOS technology is described. The PLL has a locking range of 15 to 240 MHz. The static phase error is less than 1100 ps with a peak-to-peak jitter of ±50 ps at a 100 MHz output frequency. The PLL has a resistorless architecture achieved by the implementation of feedforward current injection into the current controlled oscillator

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:30 ,  Issue: 11 )