Referenced Items are not available for this document.
A fully integrated phase-locked loop (PLL) in a digital 0.5 μm CMOS technology is described. The PLL has a locking range of 15 to 240 MHz. The static phase error is less than 1100 ps with a peak-to-peak jitter of ±50 ps at a 100 MHz output frequency. The PLL has a resistorless architecture achieved by the implementation of feedforward current injection into the current controlled oscillator
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:30
,
Issue:
11
)
Date of Publication: Nov 1995
- Page(s):
- 1259 - 1266
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 5173165
- Digital Object Identifier :
- 10.1109/4.475714
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Nov 1995
- Sponsored by :
- IEEE Solid-State Circuits Society
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