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A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL

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9 Author(s)
K. Ishibashi ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; K. Komiyaji ; H. Toyoshima ; R. Minami
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A 4-Mb (64 k×64) synchronous wave-pipeline CMOS SRAM is fabricated by 0.25-μm CMOS technology. Multiphase active pulse control (MPAC) enables fully random 300 MHz operation at 2.5 V, resulting in a bandwidth of 2.4 GB/s. The pulse is generated by multiphase PLL (MPPLL) using an array oscillator with current consumption of 7.5 mA

Published in:

IEEE Journal of Solid-State Circuits  (Volume:30 ,  Issue: 11 )