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Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs

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6 Author(s)
Yamagata, T. ; ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan ; Tomishima, S. ; Tsukude, M. ; Tsuruda, T.
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This paper describes a charge-transferred well (CTW) sensing method for high-speed array circuit operation and a level-controllable local power line (LCL) structure for high-speed/low-power operation of peripheral logic circuits, aimed at low voltage operating and/or giga-scale DRAMs. The CTW method achieves 19% faster sensing and the LCL structure realizes 42% faster peripheral logic operation than the conventional scheme, at 1.2 V in 15 Mb-level devices. The LCL structure realizes a subthreshold leakage current reduction of three or four orders of magnitude in sleep mode, compared with a conventional hierarchical power line structure. A negative-voltage word line technique that overcomes the refresh degradation resulting from reduced storage charge (Qs) at low voltage operation for improved reliability is also discussed. An experimental 1.2 V 16 Mb DRAM with a RAS access time of 49 ns has been successfully developed using these technologies and a 0.4-μm CMOS process. The chip size is 7.9×16.7 mm2 and cell size is 1.35×2.8 μm2

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Solid-State Circuits, IEEE Journal of  (Volume:30 ,  Issue: 11 )