Skip to Main Content
Bit plane coding (BPC) constitutes an important component of the EBCOT Tier-1 block of JPEG2000 encoder. This paper proposes an efficient parallel hardware structure to implement the computation intensive word level bit plane coding algorithm. The proposed architecture computes the context and decision for all bit planes in parallel. The three coding passes are merged for all bit planes in a scan while the samples are coded in sequence. The proposed parallel BPC architecture offers a speed of 31 over the serial BPC architecture. Its memory requirement is independent of the size of the code block. The speed of the proposed architecture has been shown to be significantly faster than an architecture which has been recently reported in literature. The system architecture has been functionally verified by ModelSim and synthesized by TSMC 0.25 mum vtvt CMOS cell libraries.