By Topic

High Speed and Memory Efficient Parallel Bit Plane Coding Architecture for JPEG2000

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Suman, T. ; Dept of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur ; Kumar Chatterjee, S. ; Chakrabarti, I.

Bit plane coding (BPC) constitutes an important component of the EBCOT Tier-1 block of JPEG2000 encoder. This paper proposes an efficient parallel hardware structure to implement the computation intensive word level bit plane coding algorithm. The proposed architecture computes the context and decision for all bit planes in parallel. The three coding passes are merged for all bit planes in a scan while the samples are coded in sequence. The proposed parallel BPC architecture offers a speed of 31 over the serial BPC architecture. Its memory requirement is independent of the size of the code block. The speed of the proposed architecture has been shown to be significantly faster than an architecture which has been recently reported in literature. The system architecture has been functionally verified by ModelSim and synthesized by TSMC 0.25 mum vtvt CMOS cell libraries.

Published in:

Computer Vision, Graphics & Image Processing, 2008. ICVGIP '08. Sixth Indian Conference on

Date of Conference:

16-19 Dec. 2008