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Concurrent Error Detection (CED) techniques based on hardware duplication are widely used to enhance system dependability. All CED techniques contain some form of redundancy. In this paper we present simulation results to quantitatively compare various CED schemes based on their area overhead and protection (data integrity) they provide against multiple failures. We describe some studies of parity based concurrent error detection in S-boxes. In this work substitution blocks of PP-1 block-cipher, designed for platforms with very limited resources (for example for embedded systems), are used as a case study.