By Topic

Efficient CORDIC Algorithms and Architectures for Low Area and High Throughput Implementation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Vachhani, L. ; Dept. of Electr. Eng., Indian Inst. of Technol. Madras, Chennai ; Sridharan, K. ; Meher, P.K.

This paper presents two area-efficient algorithms and their architectures based on CORDIC. While the first algorithm eliminates ROM and requires only low-complexity barrel shifters, the second eliminates barrel shifters completely. As a consequence, both the algorithms consume approximately 50% area in comparison with other CORDIC designs. Further, the proposed algorithms are applicable to the entire range of angles. The FPGA implementations consume approximately 8% LUTs of a Xilinx Spartan XC2S200E device and have a slice-delay product of about 3. Convergence proofs for the algorithms are presented. Experimental comparisons with prior CORDIC designs confirm the efficacy of the proposed designs.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:56 ,  Issue: 1 )