Parallel Correction and Adaptation Engines for I/Q Mismatch Compensation

We present a low-area implementation of an I/Q mismatch compensation (IQMC) circuit that comprises a correction engine and an adaptation engine. The correction engine performs I/Q mismatch compensation in the data path using a filter whose coefficients are updated after a programmable amount of time by a parallel adaptation engine that performs sample-by-sample off-line adaptation. This scheme allows very fast online adaptation while protecting the receiver data path from the degradations caused by a fast converging algorithm. The proposed scheme has been successfully implemented in 90-nm digital CMOS process for a low-IF quad-band GSM transceiver SoC. A single multiplier is used to perform complex multiplications for both correction and adaptation engines, resulting in a 0.025 mm
²
circuit. Image Rejection Ratio in excess of 50 dB is measured that is sufficient for IF frequencies as high as 200 kHz for GSM application.