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CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction

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3 Author(s)
Joung-Yeal Kim ; Sch. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon ; Young-Hyun Jun ; Bai-Sun Kong

A CMOS charge pump based on a transfer blocking technique and a modified precharge scheme is proposed for avoiding reversion loss and relaxing the timing restrictions imposed on input clocks. Comparison results in an 80-nm CMOS process indicate that, with no loading current, the output voltage of the proposed charge pump reaches almost 98% of the ideal boosting level with switching ripple reduced by up to 97%. They also indicate that output voltage deviations due to temperature and process variations are reduced by 24%-98% and 81%-95%, respectively.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:56 ,  Issue: 1 )