By Topic

A Comprehensive Investigation of Analog Performance for Uniaxial Strained PMOSFETs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Kuo, J.J.-Y. ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu ; Chen, W.P.-N. ; Pin Su

This paper presents a comprehensive investigation of the analog performance for uniaxial strained PMOSFETs with sub -100 nm gate length. Through a comparison between co-processed strained and unstrained devices regarding important analog metrics such as transconductance to drain current ratio (g m/I d), dc gain, linearity, low-frequency noise, and device mismatch, the impact of process-induced uniaxial strain on the analog performance of MOS devices has been assessed and analyzed. Our results indicate that, although the drain current noise spectral density and drain current mismatch of the strained device under low gate voltage overdrive are increased because of the larger gate-bias sensitivity of carrier mobility, the strained device has almost the same low frequency and mismatch performance as the unstrained one at a given g m/I d. This paper may provide insights for analog design using advanced strained devices.

Published in:

Electron Devices, IEEE Transactions on  (Volume:56 ,  Issue: 2 )