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Atomically Flat Silicon Surface and Silicon/Insulator Interface Formation Technologies for (100) Surface Orientation Large-Diameter Wafers Introducing High Performance and Low-Noise Metal–Insulator–Silicon FETs

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6 Author(s)
Rihito Kuroda ; Grad. Sch. of Eng., Tohoku Univ., Sendai ; Tomoyuki Suwa ; Akinobu Teramoto ; Rui Hasebe
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Technology to atomically flatten the silicon surface on (100) orientation large-diameter wafer and the formation technology of an atomically flat insulator film/silicon interface are developed in this paper. Atomically flat silicon surfaces composed of atomic terraces and steps are obtained on (100) orientation 200-mm-diameter wafers by annealing in pure argon ambience at 1200degC for 30 min. Atomically flat surfaces with various terrace widths and step structures are observed by atomic force microscopy. It is found that the atomic terrace width changes widely with an off angle of the wafer surface from the (100) lattice plane. It is also found that the direction of the off angle significantly affects the atomically flat surface morphology, i.e., when the directions of the off angles are parallel to the <110> directions, the step structure is composed of alternating pairs of straight and triangular steps. When the directions of the off angles are parallel to the <100> directions, the step structure is composed of only straight steps. By precise control of the off angle and the direction toward the <100> directions for a 200-mm-diameter silicon wafer, we have succeeded in fabricating an atomically flat surface with straight atomic steps and a very uniform terrace width of 140-150 nm on the entire surface of a large-diameter silicon wafer. Furthermore, it is found that only radical-reaction-based insulator film formation technology, such as oxidation utilizing oxygen radicals carried out at a low temperature (400degC ), preserves the atomic flatness of the insulator film/silicon interface. Finally, when MOSFETs are fabricated with an atomically flat interface, they exhibit near ideal subthreshold swing factors, with much smaller fluctuation, extremely lower 1/f noise, and higher MOS dielectric breakdown field intensity compared with MOSFETs fabricated with conventional technologies.

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IEEE Transactions on Electron Devices  (Volume:56 ,  Issue: 2 )