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Yield loss mechanisms in MOS-gated power devices

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2 Author(s)
P. Venkatraman ; Power Products Div., Motorola Inc., Phoenix, AZ, USA ; B. J. Baliga

Defects which cause yield loss in MOS-gated power devices are discussed. Design and fabrication of a test element group for analysis of gate to source shorts in MOS-gated power devices are described. Experimental results obtained from these test elements are presented, based upon which it is demonstrated that gate to source shorts in power MOS-gated devices occur mainly along the edge of the polysilicon gate. The contact window opening step has been found to have a strong influence on the density of gate to source shorts

Published in:

IEEE Transactions on Semiconductor Manufacturing  (Volume:8 ,  Issue: 4 )