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Power-aware soft error hardening via selective voltage scaling

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2 Author(s)
Kai-Chiang Wu ; Department of Electrical and Computer Engineering, Carnegie Mellon University, USA ; Diana Marculescu

Nanoscale integrated circuits are becoming increasingly sensitive to radiation-induced transient faults (soft errors) due to current technology scaling trends, such as shrinking feature sizes and reducing supply voltages. Soft errors, which have been a significant concern in memories, are now a main factor in reliability degradation of logic circuits. This paper presents a power-aware methodology using dual supply voltages for soft error hardening. Given a constraint on power overhead, our proposed framework can minimize the soft error rate (SER) of a circuit via selective voltage scaling. On average, circuit SER can be reduced by 33.45% for various sizes of transient glitches with only 11.74% energy increase. The overhead in normalized power-delay-area product per 1% SER reduction is 0.64%, 1.33X less than that of existing state-of-the-art approaches.

Published in:

Computer Design, 2008. ICCD 2008. IEEE International Conference on

Date of Conference:

12-15 Oct. 2008