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Test-access mechanism optimization for core-based three-dimensional SOCs

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4 Author(s)
Xiaoxia Wu ; Comput. Sci. & Eng. Dept., Pennsylvania State Univ., University Park, PA ; Yibo Chen ; Chakrabarty, K. ; Yuan Xie

Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) facilitate the modular testing of embedded cores in a core-based system-on-chip (SOC). Such a modular testing approach can also be used for emerging three-dimensional integrated circuits based on through-silicon vias (TSVs). Core-based SOCs based on 3D IC technology are being advocated as a means to continue technology scaling and overcome interconnect-related bottlenecks. We present an optimization technique for minimizing the test time for 3D core-based SOCs under constraints on the number of TSVs and the TAM bitwidth. The proposed optimization method is based on a combination of integer linear programming, LP-relaxation, and randomized rounding. Simulation results are presented for the ITC 02 SOC Test Benchmarks and the test times are compared to that obtained when methods developed earlier for two-dimensional ICs are applied to 3D ICs.

Published in:

Computer Design, 2008. ICCD 2008. IEEE International Conference on

Date of Conference:

12-15 Oct. 2008